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[招聘] Lattice招聘

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莱迪思(lattice)在上海漕河泾合川路地铁站附近,招聘如下人员,欢迎联系:764425008@qq.com

1.? ?? ?Sr. Analog Design Engineer
Accountabilities:
2 Develop novel analog/mixed signal integrated circuit IPs forhigh performance FPGA chip.
2 Candidate will focus on analog or mix signal design for highperformance, high speed input and output circuit, DDR phy circuit, high speedserdes, PLL, oscillator, BGR...
2 Development task starts from specification to final IP release.Detail work includes design spec, circuit architecture and implementation,pre-layout and post-layout simulation, behavior modeling, IP integration andsilicon bring up and debug.
Qualifications:
2 MS or PhD Degree in Electrical Engineering with an emphasis inanalog or mixed signal design
2 5 years of experience in analog or mixed signal IP developmentunder advanced CMOS process node (65nm and below)
2 Demonstrated strong analog or mixed signal IP design skills inhigh speed connectivity product development
2 Solid knowledge in analog circuit, signal processing theory andsemiconductor device physics
2 Hands on skills in circuit design, simulation, Verilog andVerilog-A behavior modeling
2 Familiar with main stream EDA tools in analog mixed signaldesign
2 Strong problem analysis and debug skill
2 Experience with one or more following areas: PLL, CDR, CTLE,BGR, DRIVER, IO, DDR, LVDS.
2 Experience working with layout team together and guide layoutoptimization to achieve high quality layout
2 Experience in product tape out and silicon bring up/debug
2 Ability to multi-tasks and set priorities with tight schedule
2 Experience working in dynamic, fast-paced company environment
2 Good oral and writing English communication skill
2.? ?? ?Sr. FPGA Circuit DesignEngineer
Accountabilities:
2 Responsible for FPGA integration custom IP design Tspec
2 Responsible for schematic ic circuit design and verification
2 Guide layout engineer to finish the IP layout design
2 Responsible for FPGA full-chip group sim (function and timing)
2 Responsible for FPGA full-chip integration
2 Responsible for FPGA bring-up supporting
Qualifications:
2 5+ relative circuit design experience
2 Familiar with digital design logic, clock design, sram design
2 Familiar with Virtuoso / Finesim design and verification tool
2 Familiar with scripts, like Perl / Python / Tcl…
2 Familiar with Verilog / Synthesis / STA
3.? ?? ?Sr. Fullchip IntegrationDesign Engineer
Accountabilities:
2 Responsible for FPGA integration Tspec
2 Responsible for FPGA integration design, and digital block RTLdesign
2 Research the schematic IP design for top integration
2 Responsible for timing constraints, synthesis, STA, low powerdesign for digital block level
2 Responsible for dft scan insertion & ATPG for digital blocklevel
2 Co-work with P&R and Layout team for the physicalimplementation of digital block and full chip
2 Responsible for chip bring up
Qualifications:
2 5+ relative full chip integration experience
2 Digital logic design capability and clock, rst, mbist relativedesign experience
2 Familiar with ASIC flow, synthesis, STA, DFT..., relative EDAtools
2 Familiar with scripts, like Perl / Python / Tcl…
2 Familiar with Verilog / Synthesis / STA
2 Familiar with Virtuoso / Spice simulation is better
4.? ?? ?Sr. Digital Design Engineer
Accountabilities:
2 Create module level target specification based on exactlyunderstanding the product requirement and full-chip target specification
2 Independently complete module design and simulation
2 Be responsible for RTL synthesis, Lint rule check and CDCcheck??
2 Support chip level STA, DFT and P&R
2 Support top level simulation, verification, and post-simulation
2 Support emulation, validation and application
2??Writedesign document and provide design report
Qualifications:
2 Have about 3-5-year working experience of digital front-enddesign
2 Master degree in EE or related fields
2 Good fundamental acknowledges in communication, computer anddigital signal processing
2 Capability to analyze the design requirement and make bestdesign trade-off
2 Understanding whole digital circuit development flow
2 Be proficient in RTL coding and high level modeling usingVerilog language
2 Capability to set up test bench for design simulation and debug
2 Understand timing constraint and timing issue fixing
2 Have experience in synthesis or static timing analysis
2 Have good communication skill in both Chinese and English
5.? ?? ?Sr. FPGA SW ValidationEngineer
Accountabilities:
2 Experienced with the process flow of EDA tools for FPGA
2 Familiar with software testing process and method
2 Write test cases in Verilog/VHDL or C/C++ to verify key featuresduring software development
2 Write scripts to improve the productivity of testing
2 Responsible for Lattice software product validation andverification
2 Responsible for Lattice FPGA product co-verification
2 Responsible for synthesis tool evaluation and testing vs 3rdparty vendor
2 Responsible for simulation tool integration testing
2 Execute QA regression on test platform and analyze the failures
2 Identify Software issue, file CRs and keep tracking CRs tillbeing verified
2 Customer issue analysis and isolation
2 Provide QA testing report to support Software release
Qualifications:
2 Bachelor degree with 5 working years or Master degree with 3working years. Majored in EE/Automation/related major is preferred.
2 Skill in digital logic circuits design with FPGA application
2 Skill in Verilog/VHDL coding
2 Familiar with embedded system
2 Skill in C/C++ coding and debugging
2 Familiar with FPGA technologies, preferably Lattice
2 Experience in applying EDA tools such as Diamond, ISE/Vivado orQuartus II
2 Experience in synthesis tools application as well as simulation tools
2 Experience in script programming (Python, Perl, Tcl or Shell andetc.)
2 Experience in operation system i.e Windows and Linux
2 Good written and verbal communication skills in English
6.? ?? ?Sr. SOC Design Engineer
Accountabilities:
2 Embedded System (SOC) design and development on Lattice FPGAdevice
2 Embedded System (SOC) integration and verification
2 Processor (CPU) IP design and verification based on use caserequirement
2 System Bus, Peripheral, Interconnect, Debug IP design and verification
2 FPGA Bit file generation and board/system level debug
2 Co-work with software engineer for embedded system setup anddebug
Qualifications:
2 Have a master's degree in ME/EE/CS
2 5+ years’ experience in Embedded System (SOC) design orprocessor design
2 Strong proficiency in Verilog/system Verilog
2 Familiar with simulation tools like Ncsim, modelsim??
2 Familiar with scripts programming (Makefile, Perl, Python etc)
2 Good understanding on system bus (AXI, AHB, Wishbone etc)
2 Experiences in one or more of the following area will be a plus:
a.RISC architecture and micro-architecture (RISC-V, ARM);
b.SOC debug system and JTAG;
c.Peripheral and legacy IP (PCIE, SPI, I2C, UART etc);
d.Embedded programming with C language;
e.ASIC or FPGA design flow;
f.Advanced verification methodology (UVM etc).
2 Must possess independent problem solving skills
2 Strong written and verbal communication skills and the abilityto work with multiple groups
2 Must be a sense of responsibility and work actively
7.? ?? ?Sr. Processor DesignEngineer
Accountabilities:
2 Processor (CPU) IP design and verification on Lattice FPGA device
2 SOC integration and verification
2 FPGA Bitfile generation and board/system level debug
2 Co-work with software engineer for embedded system setup and debug
Qualifications:
2 Havea master's degree in ME/EE/CS
2 5+years’ experience in processor(CPU) design or SOC design
2 Strongproficiency in Verilog/System Verilog
2 Familiarwith simulation tools like Ncsim, Modelsim??
2 Familiarwith Linux work station environment and script programming (Makefile, Perl,Python etc)
2 Goodunderstanding on system bus (AXI, AHB, Wishbone etc.)
2 Experiencein one or more of the following area will be a plus:
·? ?? ?? ? RISC architecture and micro-architecture (RISC-V,ARM);
·? ?? ?? ? CPU Core design;
·? ?? ?? ? CPU platform SOC integration;
·? ?? ?? ? SOC debug system and JTAG protocol;
·? ?? ?? ? Cache system design;
·? ?? ?? ? Advanced verification methodology (UVM etc.).
2 Mustpossess independent problem solving skills
2 Strongwritten and verbal communication skills and the ability to work with multiplegroups
2 Mustbe a sense of responsibility and work actively
8.? ?? ?Sr. System Solution Engineer
Accountabilities:
2 As the key contributor of System Solution team, architect SystemLevel Solution based on Lattice product, to support marketing and customerrequirements of different industries through close partnership with Sales andMarketing team.
2 Develop the collateral to promote the solutionto customer and develop the related document to guide the solutionimplementation.
2 As the expert in System solution team, to guide team members andcustomers for high-speed interface protocol design and application.
2 Work with the cross functional teams to develop System SolutionPlatform for system level performance analysis.
Qualifications:
2 BS/MS, in Communication, Microelectronics/ElectronicEngineering, Compute Science, or relevant subject.
2 BS 7+ or MS 5+ year’s FPGA/ASIC development and debuggingexperience.
2 Experienced in RTL design and debug, and familiar withsimulation tools Modelsim or NC-Verilog.
2 Good knowledge on Serdes, and experienced in high-speedinterface protocol is preferred, such as PCIE, HDMI, DP/eDP, and GBE.
2 Experienced in security network of server system, communicationnetwork, automotive network, or IoT, is preferred.
2 Expertise in encryption/decryption algorithm, able to lead theteam to develop security solution is preferred.
2 Experienced in communication, video bridge and processing, ispreferred.
2 Good communication skills in both Chinese and English.Willingness to work with teams in US, Europe, Japan, and Korea.
2 Highly organized, with attention to details, time management,and deadlines. Good team player is expected.

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